1. Field of the Invention
The present invention generally relates to a semiconductor device and a manufacturing method thereof. More particularly, the present invention relates to a chip packaging structure and a chip packaging process.
2. Description of Related Art
Compared to the conventional package technology which works with die, wafer-level package (WLP) processes the entire wafer. In other words, WLP performs back-end packaging process to a plurality of chip units at the same time. Thus, the chip packaging process is simplified, and the time and cost of the chip packaging process are reduced. That is, after the devices, circuits, and the related front-end semiconductor processes have been completed, the back-end packaging process can be directly performed over an entire carrier, and then singulation process is performed to form a plurality of chip packaging structures.
In today's developing optoelectronic industry, mature semiconductor manufacturing technologies have been widely applied to optoelectronic devices and the design of optoelectronic devices are continuously going towards minimization and multi-functionality. For example, the typical optoelectronic devices using semiconductor manufacturing process technologies include charge-coupled device (CCD), complementary metal-oxide semiconductor (CMOS) image sensor etc. Similarly, the time and cost for mass-manufacturing optoelectronic devices with foregoing wafer-level package process can also be reduced.